1. Field of the Invention
This invention relates to noncontact testing of integrated circuits, and more particularly relates to a photon assisted tunneling room-environment testing procedure by which conductive test sites of a passivated integrated circuit wafer, covered with a thin layer of insulation and a transparent conductive layer, are accessed by a pulsed laser to provide voltage-modulated photoemitted photons which tunnel through the insulation layer to the conductive layer for detection.
2. Description of the Prior Art
The following publications are representative of the prior art and scientific background:
Z. A. Weinberg and A. Hartstein, "Photon Assisted Tunneling from Aluminum into Silicon Dioxide," Solid State Communications 20, 179 (1976) describes the theory of photon assisted electron tunneling and its use in an experimental demonstration. PA0 Copending U.S. patent application of Beha, Dreyfus and Rubloff, Ser. No. 667,506 filed Nov. 1, 1984, entitled NON-CONTACT DYNAMIC TESTER FOR INTEGRATED CIRCUITS, shows a tester which allows testing in vacuum of the dynamic operation and performance of high-speed very large scale integration (VLSI) circuits, including on-chip contactless measurement of AC switching waveforms (picosecond time scales) as well as logic state evaluation (nanosecond time scales) using high energy photons (about 5-6 eV).
U.S. Pat. No. 4,051,437, Lile et al, METHOD AND APPARATUS FOR SEMICONDUCTOR PROFILING USING AN OPTICAL PROBE, Sept. 27, 1977, shows a straightforward raster scan of a semiconductor surface, by a moving spot of light, to detect anomalies by finding changes in the surface photo voltage in the surface space charge region.
U.S. Pat. No. 4,301,409, Miller et al, SOLAR CELL ANOMALY DETECTION METHOD AND APPARATUS, Nov. 17, 1981, shows a method of detecting imperfections in solar cell material by scanning with a spot of light and monitoring for variations in voltage output.
Neither Lile et al nor Miller et al measure voltages as a function of voltage-modulated photoemission.
U.S. Pat. No. 4,266,138, Nelson Jr., et al, DIAMOND TARGETS FOR PRODUCING HIGH INTENSITY SOFT X-RAYS AND A METHOD OF EXPOSING X-RAY RESISTS, May 5, 1981, shows a technique for exposing x-ray sensitive resists to carbon K x-rays using a type 2B diamond target which dissipates considerably more power and produces higher intensity x-rays than graphite targets. Nelson uses soft x-rays from the diamond target to pattern a semiconductor mask. This is a production technique, not a testing technique.
U.S. Pat. No. 4,417,948, Mayne-Banton et al, SELF-DEVELOPING PHOTOETCHING OF POLYESTERS BY FAR UV RADIATION, Nov. 29, 1983, describes a technique for photoetching polyesters by application of ultraviolet radiation in the presence of oxygen. This is also a production technique, not a testing technique.
U.S. Pat. No. 4,380,864, P. K. Das, METHOD FOR PROVIDING IN-SITU NON-DESTRUCTIVE MONITORING OF SEMICONDUCTORS DURING LASER ANNEALING PROCESS, Apr. 26, 1983, describes a technique for positioning a surface acoustic wave device adjacent to a semiconductor being annealed, affixing an electrical contact to the top surface of the semiconductor, and using a composite of the transverse surface acoustic wave and the charge carriers of the semiconductor to produce a transverse acoustoelectric voltage which thus is a function of the semiconductor conductivity. This is a contact technique, not a contactless technique, and measures semiconductor conductivity at a known location, not voltage at a known location at a known time.
U.S. Pat. No. 4,332,833, Aspnes et al, METHOD FOR OPTICAL MONITORING IN MATERIALS FABRICATION, June 1, 1982, Aspnes et al shows a technique for utilizing the sensitivity of the dielectric function of a crystal, to crystalline-amorphous-void volume fractions, and recognizing that the volume fraction vary as a function of the measured dielectric function over an appropriate range of frequencies. This range of frequencies corresponds to photon energies of approximately 1.5 electron volts to 6 electron volts. This allows a dynamic monitoring of deposition within a reactor. This is a contactless optical technique for monitoring material deposition during thin film processing; it is not a current-voltage tester.
U.S. Pat. No. 4,408,883, Iwamoto et al, APPARATUS FOR INSPECTING AVERAGE SIZE OF FUNDAMENTAL PATTERNS, Oct. 11, 1983, shows an apparatus for determining the average size of fundamental patterns by comparing Fourier transforms of pattern images in a processor, and providing actual pattern sizes. Iwamoto et al applies coherent light focussed on a target for test, and monitors the reflected images by converting them to Fourier transforms and comparing the Fourier transforms against known image patterns. This is a contactless optical technique for image recognition; it is not a current-voltage tester.
EP-A-O No. 129 508 Battelle Memorial Institute, Louis F. Pau, PROCEDE D'EXAMEN ET DE TEST D'UN DISPOSITIF ELECTRIQUE DU TYPE DES CIRCUITS INTEGRES OU IMPRIMES, Published Dec. 27, 1984, shows a technique for chip testing for foreign particles or discontinuities by irradiating a printed circuit while applying a known strobe source to the chip, and comparing the result to a standard.
G. W. Rubloff, CONTACTLESS MEASUREMENT OF VOLTAGE LEVELS USING PHOTOEMISSION, IBM Technical Bulletin, Vol. 25, No. 3A, August 1982, pp. 1171-1172, shows ultraviolet light stimulation of photoemission for contactless measurement of voltage levels, but not in the context of dynamic testing, and not with a laser (c.w., or pulsed). The author is a coinventor.
Henley, LOGIC FAILURE ANALYSIS OF VLSI CMOS USING A LASER PROBE, Spectrum Sciences, 3050 Oakmead Village Drive, Santa Clara, Calif. 95051, shows a laser contactless probe for an integrated circuit, using available pin connections to conduct stimulated current-voltage signals to a computer for analysis. Henley does not use an adjacent detector, but must dedicate a certain amount of circuitry (external to the integrated circuit under test) to the conduction of test signals. No photoemission from the circuit is created. The logic state of the integrated circuit is determined by interrupting its dynamic operation and then measuring the current transient induced in the power supply by laser light absorption in an active semiconductor region (the light does not impinge on the metal wires and nodes of the circuit); as a result, neither logic states nor AC switching waveforms are determined during dynamic operation of the circuit.
Kudo, Nihei and Kamada, COMPUTER CONTROLLED ESCA FOR NONDESTRUCTIVE SURFACE CHARACTERIZATION UTILIZING A TV-TYPE POSITION SENSITIVE DETECTOR, Rev. Scientific Instruments, Vol. 49, No. 6, June 1978, pages 756-759, American Institute of Physics, New York, U.S. Kudo et al uses an X-ray tube to excite the sample with soft X-ray photons. The intent is to excite spectroscopic light emissions for surface chemical states analysis, Kudo et al concerns itself with a different problem (spectroscopy rather than nonintrusive noncontact dynamic testing); uses different excitation (soft X-rays instead of pulsed laser); and different output processing (videcon rather than electron detector).
Ito, Goto and Furukawa, HEMISPHERICAL RETARDING TYPE ENERGY ANALYZER FOR LSI TESTING BY AN ELECTRON BEAM, Fujitsu-Scientific & Technical Journal, Vol. 19, No. 4, December 1983, pp. 431-441, Kawasaki, Japan. Ito et al shows a retarding type energy analyzer to measure the internal voltage of a large scale integrated circuit with an electron beam. Acknowledging that the hemispherical retarding type energy analyzer is conventional, Ito et al provides an improved extraction system with a buffer grid between a control grid between a control grid and an extraction grid.
Jowett, SURFACE ANALYTICAL TECHNIQUES APPLIED TO ELECTRONIC COMPONENTS, Microelectronics Journal, Vol. 11, No. 2, March/April 1980, pp. 35-40, Mackintosh Publication Ltd., Luton, UK. Jowett surveys surface analytical techniques including various e-beam, X-ray, ion and laser excitation and measurement of the results. Jowett identifies laser scanning as useful "to map DC and high frequency gain . . . , to reveal areas . . . operating in a nonlinear manner, to map temperatures . . . , to determine [and to change] internal logic states . . . , observing the circuit electrical operations and the metallisation pattern through the back of the chip."
Jowett provides a two-laser technique for ". . . observing the circuit electrical operation . . ."
Jowett states that "The effect of directing on a semiconductor light of energy greater than that of the band gap is to create electron hole pairs within the material. These can be collected as photocurrent. If the light is focussed to a spot and moved over exposed portions of a device, it is possible to learn a great deal about the internal operation of the device by interpreting the photoresponse. The interpretation is facilitated if the photoresponse is presented on the screen of a cathode ray tube whose electron beam is deflected in synchronism with the moving light spot since a two-dimensional display of the photoresponse of the device is then presented."
Jowett collects electrical signals directly from the test chip, not via photoemission. This is an optical matching technique, not a technique for noncontact dynamic testing to determine instantaneous voltage levels in a test chip during exercise.
DATA PROBE MODEL 2010 IC LOGIC LASER ANALYZER, Mitsui & Co., 1984. This paper shows a mouse driven laser beam probe using the "solar-cell" effect.
Menzel and Kubalek, SECONDARY ELECTRON DETECTION SYSTEMS FOR QUANTITATIVE VOLTAGE MEASUREMENTS, Scanning, Vol. 5.4, 151-171 (1983). Menzel et al shows e-beam probed voltage measurements using retarding field analyzers for secondary electrons.
U.S. Pat. No. 4,417,203, Pfeiffer et al, SYSTEM FOR CONTACTLESS ELECTRICAL PROPERTY TESTING OF MULTI-LAYER CERAMICS, Nov. 22, 1983, describes an electron beam system for noncontact testing of conductors embedded in dielectric material. The entire surface is charged by a wide-focus e-beam, and a single conductor, available at the surface, is activated by a sharp focus e-beam probe at its surface pad. The resulting difference in secondary emission is used to find opens and shorts.
U.S. Pat. No. 4,415,851, Langner et al, SYSTEM FOR CONTACTLESS TESTING OF MULTI-LAYER CERAMICS, Nov. 15, 1983, describes an e-beam tester in which a wide-focus e-beam at the back of a chip coacts with a sharp-focus e-beam probe at the front, to find back-to-front conductive paths by enhanced secondary emission.
U.S. Pat. No. 4,419,530, Nath, SOLAR CELL AND METHODS FOR PRODUCING SAME, Dec. 6, 1983, describes a technique for electrically isolating areas of a large semiconductor solar cell for fault bypass.
U.S. Pat. No. 4,296,372, Feuerbaum, TECHNIQUES FOR IMPRESSING A VOLTAGE WITH AN ELECTRON BEAM, Oct. 20, 1981, describes a technique of continuity testing a conductor in a passivated semiconductor chip, using a metal film over the passivating layer, and an e-beam probe to connect the metal film to a passivated conductor via a diffusion cloud. The result is a conductive path from metallic overlayer to buried conductor, permitting probing through the insulating layer via the e-beam.
Electron beam testing methods, also known, require surface availability of metal conductor points and are therefore inadequate for testing of passivated circuits. Furthermore, the electron beam causes damage to passivating layer materials such as oxides and must therefore be carefully directed away from such areas even in current electron-beam testing of metal points available at the surface.
The prior art does not teach nor suggest the invention, which permits room-environment non-contact testing even though the integrated circuit be passivated by an insulation layer, does not require high energy beams, and does not require contacts open to the surface.